1. Field
The present invention is generally related to semiconductor technology and, more particularly, is related to a method for removing defects from a surface of a semiconductor wafer without affecting the surrounding non-defective regions of the semiconductor wafer.
2. Related Prior Art
Growth defects on the surface of a semiconductor wafer are typically generated during the growth of epitaxial layers or epilayers and are the result of effusion cell spitting during molecular beam epitaxy or from interference during the growth of the epilayer due to impurities on the surface of the substrate or incomplete oxide desorption from the surface of the substrate prior to growth. Such unwanted defects are an integral part of the semiconductor wafer surface and are composed of the same material as the surrounding active device layers. See, for example, E. H. C. Parker, “The Technology and Physics of Molecular Beam Epitaxy” pages 90-93, Plenum Press (1985).
The defects are known to adversely affect the ability to join surfaces by wafer bonding and negatively affect the yield of integrated circuit fabrication. In particular, in the case of wafer bonding, protruding defects cause the bonding wafers to deform around them forming circularly unbonded interface areas or voids. The unbonded areas resulting from even small protuberances can be large. For example, a defect of about 1 micron in height can lead to an unbonded area with a diameter of about 0.3 cm for typical semiconductor wafers. See, for example, Q.-Y. Tong, U. Gösele, “Science and Technology of Semiconductor Wafer Bonding”, Chapter 3, John Wiley and Sons (1999).
FIG. 1 shows a theoretical plot of the void area between bonded wafers (vertical axis, in centimeters) as a function of the height of the protruding defects (horizontal axis, in microns). More in particular, FIG. 1 shows the non-bond void radius as a function of the height of a protruding defect between the surfaces of a 300 micron thick GaSb wafer and a 330 micron thick sapphire wafer. The continuous line represents the theoretical progress of the graph, while the circles above the continuous line are experimental data, derived from the physical properties of sapphire and GaSb. Bond energy was measured experimentally by the crack method. Therefore, FIG. 1 shows that the higher the height of the protruding defects, the bigger the deformation.
The need to eliminate growth defects is thus critical to the success of applying wafer-bonding methods to III-V semiconductor materials.
A first known method for removing such defects is chemical-mechanical polishing (CMP). CMP is a planarization technique whereby a wafer with an uneven surface is polished using an abrasive slurry. Oxide, polysilicon, and metal topography can be planarized using this technique. CMP has a number of disadvantages when applied to the removal of growth defects from epilayers. A first disadvantage is due to the inadvertent thinning of critical thickness epilayers during the defect removal process. This is due to the fact that defects are usually about 1-10 microns high and epilayers are about 10-500 Angstroms thick. A second disadvantage is the need of cleaning the polished wafer surface after applying the slurry. A third disadvantage is due to the non-uniform etching of the wafer surface due to the random positions of the defects.
A second known method for removing defects on the surface of a semiconductor wafer is known as planarization etch back process. In the planarization etch back process, hilly contours left behind by conventional chemical vapor oxide deposition (CVD) techniques are planarized by applying spin-on-glasses (SOG) or sacrificial resist layers, after which both sacrificial layer and oxide are etched back. The etch-back process can be adjusted by modifying the reactive ion etching (RIE) chemistry, to cause the sacrificial layer and the underlying oxide film to etch at similar rates. A first disadvantage of this process is that suitable RIE etching chemistries must be found for each defect material and sacrificial layer combination. A second disadvantage of this process is that a complete removal of defects from the structures requires etching of the entire epilayer surface that may result in surface roughening or partial removal of the thin epilayers.
The drawbacks of the above mentioned direct planarization techniques also depend on the kind and distribution of the defects on the surface of a semiconductor wafer. Such defects typically range in size from 1-100 microns and in densities from 1-100/cm2 and are non-uniformly distributed over the wafer surface. Other possible techniques such as serial etching methods (FIB, laser ablation, etc) are too expensive or time-intensive for the large numbers and random distribution of the defects.
Therefore, there is a need for a method which prevents inadvertent thinning of epilayers during defect removal and which at the same time allows removal of the defects.